The disclosure relates to a fabrication technology of a semiconductor device, and more particularly, to a semiconductor device with a channel formed in a vertical direction and a method of fabricating the same.
It has been known to the inventors that a semiconductor device, in order to reduce its size, may have a channel formed in a vertical direction by arranging a source and a drain within an active region in the vertical direction.
FIGS. 1A to 1C are schematic views that illustrate a method, known to the inventors, of fabricating a semiconductor device with such a channel formed in the vertical direction.
Referring to FIG. 1A, a pillar head 13 is formed in a substrate 11 using a plurality of hard mask patterns 12, and a pillar neck 15 is formed in the substrate 11 using a sidewall protection layer 14 formed on sidewalls of the hard mask pattern 12 and the pillar head 13. Hereinafter, the pillar head 13 and the pillar neck 15 are referred to as a pillar pattern. An impurity region 16 is formed by doping the substrate 11 between adjacent pillar patterns with impurities, and a gate insulation layer 17 and a gate electrode 18 are formed to surround the pillar neck 15. A capping layer 19 is formed on the substrate 11.
Referring to FIG. 1B, the capping layer 19 over the substrate 11 is selectively removed to partially expose the substrate 11, and a trench is formed in the exposed substrate 11. A separation layer 20 filling the trench is formed to separate the impurity region 16. The separated impurity region 16A is referred to as a buried bit line. The capping layer 19 is etched by a wet etch process to expose the gate electrode 18.
Referring to FIG. 1C, a conductive layer 21 is deposited over the substrate 11, and an etch-back process is performed to form a damascene word line 21A contacting the gate electrode 18. Impurities are doped into the pillar head 13, and a capacitor contacting the pillar head 13 is formed, thereby obtaining a semiconductor device with a channel formed in a vertical direction.
In this known process, only the capping layer 19 formed on the sides of the gate electrode 18 should be selectively removed in the process of exposing the gate electrode 18. However, since the wet etch process is used as the removal process, the capping layer 19 formed on the sidewall protection layer 14 is also removed. Furthermore, the capping layer 19 formed on one or more sides of the separation layer 20 may also be accidentally removed.
Therefore, in forming the damascene word line 21A, the sidewall protection layer 14 is excessively lost, so that the pillar pattern may be exposed to the outside, as indicated by the reference symbol “F1”. Further, if the capping layer 19 formed on the sides of the separation layer 20 is accidentally removed during the wet etch process, the buried bit line 16A and the damascene word line 21A may be shorted to each other, as indicated by the reference symbol “F2”.